Quick Start Guide

1. Grab the latest firmware here on the sensenig/irig_rearrange branch. Requires a CERN computing account. The README in the root directory of the branch includes the directions to clone and build the firmware.
2. The latest control software can be found here on the sensenig/gib_irig branch. Instructions to compile the software are included in the repository.
3. Assuming successful fimrware build and FPGA programming and compilation of the software, the next step is configuration.

Make sure a connection is made to the board at IP address 192.168.200.26,

sudo ifconfig <eth_adapter> up 192.168.200.1
ping 192.168.200.26

After the conection is made, a basic script to reset and configure the GIB can be found in tests/scripts/gib and run with,

python gib_setup.py

The script will do the following:

1. Reset
   1. The firmware
   2. The components on the GIB
2. Configure
   1. The GPS clock translator
   2. The clock generator (SI5395)
   3. Enable all SFP transmit
   4. Select recovered clock capture edge
3. Status
   1. Read frequency counters

If you made it to this point the GIB should be ready to generate timing protocol data which is syncronized to the 10MHz GPS clock, if said clock is connected. The firmware has 1 master block and 2 endpoint blocks which can be controlled by the standard dtsbutler commands. The firmware

• Outputs clock/data in the timing protocol from all 6 SFPs, generated by the master block.
• Receives recovered clock and data in the endpoint, from SFP 1 and 2.

The master block can be synchronized to the curent time and configured with

dtsbutler mst GIB_PRIMARY timesync
dtsbutler mst GIB_PRIMARY part 0 configure

The endpoints 0 and 1 can be enabled with,

dtsbutler ep GIB_PRIMARY <endpoint #> enable

The master and endpoint’s status can be monitored with

dtsbutler mst GIB_PRIMARY part 0 status
dtsbutler ep GIB_PRIMARY <endpoint #> status